1. Field of the Invention
This invention pertains in general to a semiconductor device, and, more particularly, to an electrostatic discharge protection circuit using a stacked-transistor-triggered rectifier device.
2. Background of the Invention
A semiconductor integrated circuit (IC) is generally susceptible to an electrostatic discharge (ESD) event that may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is discharged through the IC. Protecting an IC from an ESD event, therefore, is an important factor to be considered in IC design. In deep sub-micron, or small geometry, complementary metal oxide silicon (CMOS) technology, the protection of an IC becomes an even more important issue due to the implementation of thin oxide layers in such ICs. As oxide layers become thinner, the voltage margin between oxide breakdown voltage and drain snapback breakdown voltage of a metal-oxide-silicon (xe2x80x9cMOSxe2x80x9d) transistor is reduced.
It also follows that transistors having a smaller geometry operate in different voltage levels than transistors with a larger geometry, and the transistors with a smaller geometry cannot withstand an ESD level tolerable to transistors with a larger geometry. As designers continue to design ICs with increasingly smaller geometries, it is inevitable that ICs having transistors with different geometries will be interconnected for a variety of applications. Therefore, with a mix of different operating voltage levels, input/output (I/O) pads of mixed voltage ICs must be designed to avoid electrical overstress and prevent undesirable current leakage paths. An ESD protection circuit must also satisfy the same I/O interface conditions and constraints, and be able to be triggered so as to prevent the internal circuitry from being damaged. Many schemes have been implemented to protect a mixed voltage IC from an ESD event.
FIG. 1 is a reproduction of FIG. 2 of U.S. Pat. No. 5,932,918 to Krakauer. Krakauer describes an ESD protection circuit for mixed voltage I/O circuits. FIG. 1 shows an ESD protection device using two n-type MOS (NMOS) transistors stacked in a cascade configuration at the I/O buffer to protect a mixed voltage IC. The two stacked-NMOS transistors have common nodes formed by a shared diffusion. However, due to the reduced gate oxide breakdown voltage in a mixed I/O application, the MOS gate oxide of the I/O buffer might be damaged under an ESD event before the lateral NPN bipolar transistor in the stacked NMOS transistors can be turned on to divert the ESD current away from the internal circuits.
It is accordingly a primary object of the invention to provide an electrostatic discharge protection circuit using a stacked-transistor-triggered silicon controlled rectifier device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
In accordance with the invention, there is provided an electrostatic discharge protection circuit that includes a rectifier, having an anode and a cathode, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the first p-type portion is coupled to the anode and the second n-type portion is coupled to the cathode, a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier, a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second n-type portion of the rectifier, and a voltage coupling circuit having a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the first terminal is coupled to the anode of the rectifier, the second and the third terminals are respectively coupled to the gate terminals of the first and second transistors, and the fourth terminal is coupled to the cathode.
In one aspect, the voltage coupling circuit provides a first voltage signal to the gate of the first transistor and a second voltage signal to the gate of the second transistor to turn on the rectifier.
In another aspect, the voltage coupling circuit includes a first capacitor coupled to the first terminal of the voltage coupling circuit and the gate terminal of the first transistor, and a second capacitor coupled to the first terminal of the voltage coupling circuit and the gate terminal of the second transistor.
In yet another aspect, the voltage coupling circuit further includes a clamping circuit, a first resistor and a second resistor, the clamping circuit coupled to the first resistor and the gate terminal of the first transistor, and the first resistor coupled to the clamping circuit and the cathode of the rectifier, and the second resistor coupled to the gate terminal of the second transistor and the cathode of the rectifier.
In still another aspect, the clamping circuit clamps the first voltage signal provided to the gate terminal of the first transistor, and the first and second resistors, in conjunction with the first and second capacitors, control a time delay to turn on the rectifier.
Also in accordance with the present invention, there is provided an integrated circuit that includes a signal pad for receiving and outputting a signal, a rectifier with an anode and a cathode including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the anode of the rectifier is coupled to the signal pad, a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier, and a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second n-type portion of the rectifier, and the second terminal is coupled to the second terminal of the first transistor.
In one aspect, the circuit further comprises an output buffer having a first terminal and a second terminal, wherein the first terminal is coupled to the signal pad and the second terminal is coupled to the first capacitor and the second capacitor.
Additionally in accordance with the present invention, there is provided an integrated circuit that includes an output buffer having a first terminal and a second terminal, a rectifier with an anode and a cathode including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the anode of the rectifier is coupled to the first terminal of the output buffer, a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier, and a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second-type portion of the rectifier, and the second terminal is coupled to the second terminal of the first transistor.
Also in accordance with the present invention, there is provided an integrated circuit that includes a signal pad for receiving and outputting a signal, an output buffer having a first terminal and a second terminal, wherein the second terminal is coupled to the signal pad, a rectifier, having an anode and a cathode, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the first p-type portion is coupled to the anode, the second n-type portion is coupled to the cathode, the anode is coupled to the first terminal of the output buffer, and the cathode is coupled to ground, a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier, a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second n-type portion of the rectifier, and a voltage coupling circuit having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal is coupled to the anode of the rectifier, the second and the third terminals are respectively coupled to the gate terminals of the first and second transistor, and the fourth terminal is coupled to the cathode of the rectifier.
Additionally in accordance with the present invention, there is provided an integrated circuit that includes a signal pad for receiving and outputting a signal, an output buffer having a first terminal and a second terminal, wherein the second terminal is coupled to the signal pad, a rectifier with an anode and a cathode including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the anode of the rectifier is coupled to the second terminal of the output buffer and the cathode of the rectifier is coupled to ground, a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier, a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second n-type portion of the rectifier; and a voltage coupling circuit having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal is coupled to the first terminal of the output buffer, the second and the third terminals are respectively coupled to the gate terminals of the first and second transistor, and the fourth terminal is coupled to the cathode of the rectifier.
Further in accordance with the present invention, there is provided a method for protecting an integrated circuit with a dual input/output pad from electrostatic discharge that includes providing a rectifier having a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, providing a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier, and providing a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second n-type portion of the rectifier, and the second terminal is coupled to the second terminal of the first transistor.
In one aspect, the method further includes a step of providing a first voltage signal to the gate of the first transistor and a second voltage signal to the gate of the second transistor to turn on the rectifier.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.